The present invention relates to a semiconductor memory device and more specifically to the circuit arrangement of a semiconductor memory device operations of which are synchronized with a high-frequency clock signal. This application is based on Japanese Patent Application No. 10-364613, filed Dec. 22, 1998, the content of which is incorporated herein by reference.
Such a semiconductor memory device as is synchronized with a high-frequency clock signal is referred hereinafter to as a synchronous memory. The circuit arrangement of a conventional synchronous memory 100 is shown in FIG. 1. The memory 100 is roughly divided into a memory core section 101 and an I/F circuit section.
The I/F circuit section includes right and left shift register sections 102 adjacent to the memory core section 101, right and left input/output (I/O) circuits 106 corresponding to the right and left shift register sections, a delayed locked loop (DLL) circuit 111, and a control logic circuit 112.
The DLL circuit 111 produces an internal write data control clock signal rclk in synchronization with an externally applied write clock signal RXCLK and an internal read data control clock signal tclk in synchronization with an externally applied read clock signal TXCLK.
The control logic circuit 112 performs logical operations on a protocol entered through an external command signal COMMAND to produce control signals for the memory.
The right and left I/O circuits 106 are responsive to the internal write data control signal rclk to take in serial write data DQ&lt;0:7&gt; and DQ&lt;8:15&gt;, respectively, from external I/O data lines and then output internal serial write data eWrite and oWrite to the shift register sections 102 each consisting of plural shift registers.
Further, the right and left I/O circuits are responsive to the internal read data control signal tclk to take in internal serial read data eRead and oRead from the left and right shift register sections, respectively, and then output serial read data DQ&lt;0:7&gt; and DQ&lt;8:15&gt;, respectively, onto the external I/O data lines.
Here, &lt;0:7&gt; and &lt;8:15&gt; represent the low-order eight bits and the high-order eight bits, respectively, of 16-bit data. The letters e and o affixed to Read and Write represent even-numbered and odd-numbered bits of data, respectively.
The shift register sections 102 are each responsive to a control signal to take in internal parallel read data RD&lt;0:7&gt; output from the memory core section 101 in a read operation and to write internal parallel write data WD&lt;0:7&gt; output therefrom into the memory core section in a write operation.
Thus, the right and left shift registers 102 convert internal parallel read data RD&lt;0:7&gt; read from the memory core section 101 into internal serial read data eRead and oRead at read time and convert internal serial write data eWrite and oWrite from the I/O circuits 106 into internal parallel write data WD&lt;0:7&gt; at write time.
The memory core section 101 includes, as in a normal DRAM circuit, a memory cell array, a sense amplifier, a row decoder, a column decoder, a redundancy fuse, and a DQ buffer.
In FIG. 2, there is illustrated, in the layout of the conventional synchronous memory, the flow of data from the memory core section 101 to the I/O circuits 106 with conversion from parallel form to serial form by the shift register sections 102. Here, the right and left I/O circuits 106 included in a peripheral circuit section 105 enclosed with dashed lines are consecutively numbered 0 through 7 and 8 through 15.
In writing into the memory core section 101, serial write data from the I/O circuits 106 are entered into the shift register sections 102 for conversion into parallel write data and the resulting parallel write data are written into the memory core section 101.
Thus, the flow of data in a write operation is the reverse of that in a read operation. In FIG. 2, therefore, there is illustrated the flow of data in a read operation by way of example.
In FIG. 2, four memory core sections 101 are placed above and below the peripheral circuit section 105. The left-hand memory core sections 101 are each allocated areas for eight bits in correspondence with the left-hand 8-bit I/O circuit 106 assigned consecutive numbers 0 through 7. Likewise, the right-hand memory core sections 101 are each allocated areas for eight bits in correspondence with the right-hand 8-bit I/O circuit 106 assigned consecutive numbers 8 through 15. As a result, a 16-bit synchronous memory is constituted as a whole.
In this manner, the cell array is allocated areas from (I/O)0&lt;0:7&gt; to (I/O)15&lt;0:7&gt; each of eight bits as shown in FIG. 2. If the synchronous memory is active, then either upper left and lower right memory core sections or lower left and upper right ones will be selected in combination by an address signal.
Data read from each memory core section in a parallel form, eight bits at a time, is converted to 8-bit serial data in the corresponding shift register section 102. The shift register section 102 is illustrated in detail in FIGS. 3A and 3B.
FIG. 3A shows the shift register section 102 in enlarged form. The shift register section 102 has shift registers 102a each corresponding to a respective one of the I/O circuits (I/O)0 through (I/O)7. Odd-numbered bits of data and even-numbered bits of data (hereinafter referred simply as to even and odd data) are shifted in the shift register section in synchronization with rising and falling edges, respectively, of the internal read data control clock tclk.
That is, eight-bit parallel read data of RD0&lt;0:7&gt; to RD7&lt;0:7&gt; read from the memory core section are entered into the shift registers 102a and odd serial read data of oRead0 to oRead7 and even serial read data of eRead0 to eRead7 are read from the shift registers 102a.
Odd serial write data of oWrite0 to oWrite7 and even serial write data of eWrite0 to eWrite7 are entered into the shift registers 102a and 8-bit parallel write data of WD0&lt;0:7&gt; to WD7&lt;0:7&gt; are output from the shift registers.
FIG. 3B shows the circuit arrangement of the shift register 102a, which includes a read register 107 and a write register 108.
The read register 107 includes first and second shift registers. The first shift register includes four cascade-connected flip-flops (FFs) 109 that receive odd parallel read data RD&lt;1&gt;, RD&lt;3&gt;, RD&lt;5&gt;, and RD&lt;7&gt; and output serial read data oRead. The second shift register includes four cascade-connected FFs 110 that receive even parallel read data RD&lt;0&gt;, RD&lt;2&gt;, RD&lt;4&gt;, and RD&lt;6&gt; and output serial read data eRead.
Likewise, the write register 108 includes first and second shift registers. The first shift register includes four cascade-connected FFs 109 that receive odd serial write data oWrite and output odd parallel write data WD&lt;1&gt;, WD&lt;3&gt;, WD&lt;5&gt; and WD&lt;7&gt;. The second shift register includes four cascade-connected FFs 110 that receive even serial write data eWrite and output even parallel write data WD&lt;0&gt;, WD&lt;2&gt;, WD&lt;4&gt; and WD&lt;6&gt;.
Thus, the read register 107 and the write register 108 provide parallel-to-serial conversion and serial-to-parallel conversion, respectively.
Next, reference will be made to timing diagrams of FIGS. 4 through 7 to describe read and write operations of the synchronous memory in terms of one memory core section 101 and its associated shift register section 102 and I/O circuit 106.
First, an example of a read operation will be described with reference to FIG. 4. Eight-bit parallel read data RD&lt;0:7&gt; is output from a memory core section 101 at a fixed time after the entry of a read command signal COMMAND.
The odd bits 1, 3, 5 and 7 of the 8-bit parallel read data RD&lt;0:7&gt; are applied to the inputs of the respective FFs 109 in the read register 107 and then clocked out of the read register in synchronization with rising edges of the internal read data control clock signal tclk, whereby conversion into 4-bit serial read data oRead is performed.
On the other hand, the even-numbered bits 0, 2, 4 and 6 of the 8-bit parallel read data RD&lt;0:7&gt; are applied to the inputs of the respective FFs 110 in the read register 107 and then clocked out of the read register in synchronization with falling edges of the internal read data control clock signal tclk, whereby conversion into 4-bit serial read data eRead is performed.
These serial read data oRead and eRead are then combined, so that 8-bit serial read data including bits numbered 0 through 7 is output to outside through the associated I/O circuit 106 of FIG. 2. In this manner, 8-bit serial read data is output in four cycles of the clock signal tclk. That is, 4-bit read data oRead and eRead can be alternately output using rising and falling edges of the clock signal tclk.
Another example of a read operation is illustrated in FIG. 5, which is a timing diagram for parallel-to-serial conversion using only rising edges of the internal read data control clock signal tclk. This approach requires eight cycles of the clock signal tclk for parallel-to-serial conversion of 8-bit data unlike the FIG. 4 case where both the rising and falling edges of the clock signal tclk are used.
Next, an example of a write operation will be described with reference to FIG. 6. Eight-bit serial write data is output from an I/O circuit at a fixed time after the entry of a write command signal COMMAND.
The even-numbered bits 0, 2, 4 and 6 of 8-bit serial write data from the I/O circuit are sequentially applied to the input of cascade connection of the FFs 110 in the write register 108 and then clocked into the write register in synchronization with rising edges of the internal write data control clock signal rclk, whereby conversion into 4-bit parallel write data ewrite is performed.
On the other hand, the odd-numbered bits 1, 3, 5 and 7 of the 8-bit serial write data from the I/O circuit are sequentially applied to the input of cascade connection of the FFs 109 in the write register 108 and then clocked into the write register in synchronization with falling edges of the internal write data control clock signal rclk, whereby conversion into 4-bit parallel write data owrite is performed.
By combining the outputs of the FFs 109 and 110 in the write register 108, serial-to-parallel converted write data WD&lt;0:7&gt; including bits numbered 0 through 7 is output.
Another example of a write operation is illustrated in FIG. 7, which is a timing diagram for serial-to-parallel conversion based on only rising edges of the internal write data control clock signal rclk. This approach requires eight cycles of the clock signal rclk for serial-to-parallel conversion of 8-bit data unlike the case of FIG. 6 where both the rising and falling edges of the clock signal rclk are used.
Next, the configuration of the conventional synchronous memory will be described with reference to FIGS. 8A and 8B. FIG. 8A shows the pattern layout of the main circuit of the memory. Though not shown, pads connected to input/output terminals are placed in the middle of the chip.
The I/O circuits 106 are placed on the right and left of the DLL circuit 111. The control logic circuit 112 is placed above the DLL circuit. The shift register sections 102 are placed above the control logic circuit 112 and below the DLL circuit 111 and the I/O circuits 106 for data transfer to and from the memory sections 101 as indicated by arrows.
DQ buffers 103 and redundancy fuse circuits 104 are placed adjacent to the shift register sections 102. The redundancy fuse circuits are adapted to improve the manufacturing yield by providing redundancy for the memory core sections 101 and removing failed bits.
By placing each memory core section 101 and its associated shift register section 102 in the upper and lower portions of the chip symmetrically with respect to the central line, data lines and signal lines between each memory core section and its associated shift register section can be made symmetrical with respect to the central line and transfer times of data and signals over the data lines and signal lines in the upper and lower portions can be made equal to each other. The margin of read and write operations can therefore be improved. However, this configuration increases the area of the chip because of need of the two upper and lower shift register sections.
FIG. 8B is a block diagram of the memory core section 101. As with a normal semiconductor memory device, the memory core section 101 includes the DQ buffer 103, the fuse circuit 104, a memory cell array 113, a sense amplifier 114, a column decoder 115, and a row decoder 116. ADD indicates an address signal, RD read data, and WD write data.
The pattern layout can be modified such that the upper and lower memory core sections 101 share one shift register section 102. This conventional example is shown in FIG. 9. With this modified layout, a reduction in the chip area can be expected in comparison with the layout of FIG. 8, but the length of data lines and signal lines between the shared shift register section and the upper memory core section and the length of those between the shift register section and the lower memory core section will become different from each other. For this reason, a disadvantage arises in that the margin of operations of reading from and writing into the memory core section associated with longer and different length interconnections is reduced.